soft-core
英 [ˈsɒft kɔː(r)]
美 [ˈsɔːft kɔːr]
adj. 软性色情的; (性描写等)隐晦的，含蓄的
牛津词典
adj.
- 软性色情的；（性描写等）隐晦的，含蓄的
showing or describing sexual activity without being too detailed or shocking
柯林斯词典
- (性描写)非赤裸裸的，较隐晦的
Soft-corepornography shows or describes sex, but not very violent or unpleasant sex, or not in a very detailed way.
双语例句
- SOPC includes soft-core or hard-core CPU 、 memory 、 I/ O and programmable logic resource, which has all the advantage of SOC 、 PLD and FPGA.
SOPC综合了SOC、PLD和FPGA的优点，集成了硬核或软核CPU、存储器、I/O以及可编程逻辑。 - To solute the problem, the idea of kernel hardware design has been put forward. System architecture is divided into soft-core and hardcore. Hardcore will manage application tasks as a coprocessor to improve the real time of system.
针对实时性问题，提出将内核硬件化设计的思想，将系统的体系结构划分为软核和硬核，硬核作为协处理器管理应用任务，提高系统的实时性，使系统的性能得到明显的提高。 - Then, through the embedded soft-core processor technology based on FPGA, entire system the control, and processing and transmission of data of were achieved by using the co-design approach of hardware and software.
然后，通过基于FPGA的嵌入式软核处理器技术，采用软硬件协同设计的方法，实现对整个系统功能的控制及数据的处理与发送。 - For the digital part, this design is mean to construct the SOPC system in the FPGA, embedded Nios II soft-core processor to control the operation of the entire system.
对于数字部分，在FPGA内构建SOPC系统，嵌入NIOSii软核处理器对整个系统进行控制。 - Nios II soft-core processor implanted into FPGA as the control chip controls and preprocesses the data of the entire image acquisition system.
采用FPGA作为控制芯片，在其中植入NiosⅡ软核处理器以对整个图像采集系统的数据进行控制和预处理。 - Design of an Ethernet Interface Based on the Nios Soft-core Processor
基于Nios软核处理器的以太网接口设计 - According to the structure model of data acquisition and processing system connected by Ethernet, the network interface module based on the Nios soft-core system is designed to construct the network data acquisition system.
为构建网络化的数据采集系统，根据数据采集模块与处理控制模块通过以太网相连接的结构模型，设计了基于Nios软核系统的嵌入式以太网网络接口模块。 - In practice, the designer can use this soft-core as a communication module through the FPGA implementation or to quickly build a Field Bus communication system to realize flexible CAN bus interface solutions.
在实际应用中设计者可以将此软核作为通讯模块通过FPGA实现，或者快速搭建现场总线通信系统，实现灵活的CAN总线接口方案。 - It inherits the hardcore, soft-core, DSP, memory, peripheral I/ O and programmable logic.
它继承了硬核、软核、DSP、存储器外围I∕O及可编程逻辑。 - With the establishing of verification and test platform for SDH chip, We realize the function simulation, timing simulation and performance test of the IP soft-core.
通过建立SDH芯片验证平台和SDH芯片测试平台，实现IP软核的功能仿真、时序仿真和芯片性能测试。